CFDCs are important components for online testing in systems designed for high reliability, high availability, and/or systems designed to be testable so that a particular system component which is faulty can be replaced, such systems as ASICs, Printed Circuit Boards (PCBs) and digital systems such as electronic switching systems (such systems are hereinafter referred to as ASIC systems). CFDCs are typically incorporated into ASIC systems to test predetermined components of such systems for errors and to support the ASIC system's maintenance operations.
Since CFDCs identify errors in ASIC system components, there is a need for a systematic error reporting mechanism. Maintenance registers provide such a reporting mechanism. The primary maintenance register for supporting the CFDCs is an error source register (ESR) which latches and holds error data from the CFDCs. The error data indicates errors identified by the CFDCs for predetermined components in the ASIC system. Additional maintenance registers, namely a mask (MASK) register and a diagnostic control register (DCR), as well as interrupt circuits, namely an interrupt (INT) circuit with or without a priority encoded interrupt (PEINT) circuit, can be added to the ESR. These registers and circuits provide additional functionality in supporting the CFDCs. Namely, the MASK register and the interrupt circuits support the ESR in prioritizing the reporting of errors, and the DCR supports testing the CFDCs themselves to ensure that they are fault-free. Either the ESR alone, or in combination with any of the MASK, DCR or the INT circuit (with or without the PEINT circuit), is hereinafter referred to as the maintenance register assembly.
The functions performed by the ESR, MASK register and the interrupt circuits described above occur during online testing. "Online testing," performed by online testing devices (e.g., the CFDCs) during the main operations of the ASIC system, is the testing of components which perform the system's main operations. Online testing ensures that the components are fault-free. During online testing, the ASIC system components are tested by the CFDCs and the results of such testing are latched by the ESR. Also, either the ESR alone, or in combination with the MASK register and/or the interrupt circuits, reports errors to the maintenance application of the ASIC system. For online testing functions, the maintenance register assembly is controlled by the main operations of the ASIC system.
"Offline testing," performed in parallel with or independently of the main operations of the ASIC system, is the testing of components which perform functions separate from the system's main operations, e.g., testing of the CFDCs and maintenance register assembly. Offline testing ensures that such components are fault-free. This is in effect a second level of testing comprising testing the online testing devices themselves. In addition, the DCR operates during offline testing. For offline testing functions, the assembly is not controlled by the ASIC system's main operations. Rather it is controlled by a maintenance application, which can be part of the ASIC system, or another maintenance application outside the control of the ASIC system, e.g, Automatic Test Equipment application or a user driven application. During offline testing, the maintenance register assembly does not communicate directly with the maintenance application controlling it. Rather, historically, a traditional system interface has been used to connect the maintenance register assembly and the maintenance application.
However, there are several disadvantages of using the traditional system interface between the maintenance register assembly and the maintenance application. They are based on the contribution of the assembly to the area overhead of the ASIC system in which the assembly is implemented. Area overhead includes the physical (i.e., hardware) resources used for operations of the ASIC system as well as software resources. While the CFDC support functions provided by the assembly are essential to the ASIC system operation, the assembly can have a significant impact on such area overhead.
The traditional interface requires an input and an output pin for each bit of each maintenance register in order to access the data bits stored in each such register. For example, where the MASK register is a 20 bit wide register, 40 pins are needed on the maintenance register assembly (20 input and 20 output pins) to access the register's data. In addition, with a 20 bit wide MASK register, the ESR and DCR also contain 20 bits (since the functionality of the maintenance registers requires that the MASK register and the DCR have the same configuration, including bit width, as the ESR). Therefore, the number of pins on the assembly necessary to access the contents of the registers is 120. The necessity of two pins per bit for each maintenance register of the assembly incurs a significant area overhead penalty for the ASIC system. Also, ongoing developments for increasing the functionality of ASIC systems by adding system components further increases the bit width of the registers. This is because the bit width of the ESR equals the number of components which the CFDCs test. As a result, there is an ongoing need to add to the bit width of the maintenance registers in the assembly and, accordingly, further increase the overhead area penalty with the use of the traditional system interface.
Another disadvantage of using the traditional system interface is that in order to avoid the overhead penalty of two pins per bit for each maintenance register, multiple pins have been abandoned in favor of the traditional interface accessing solely the ESR or a reduced amount of data from such register. That is, instead of accessing the contents of each register, the traditional interface accesses solely the data bits of the ESR. Alternatively, instead of accessing the entire contents of the ESR to identify each CFDC (and by extension, each ASIC system component) producing an error, the traditional interface accesses an output pin for limited information as to the existence of an error in any CFDC. For example, the ESR can indicate the existence of an error on a single output pin by providing the result of logically ORing each data bit in the register, where an error is represented by a binary "one" value. These approaches result in lowering the overhead penalty. However, such reduction is at the expense of accessing the MASK register and the DCR and of providing sufficient information to identify the components of the ASIC system in which errors are detected.
Offline testing using the traditional interface either incurs significant overhead penalty or, where such penalty is reduced by limiting access solely to the ESR or to limited information about the existence of an error from the ESR, results in insufficient testing of the assembly. Accordingly, there is a need to improve the interface used for offline testing of the maintenance register assembly in order to reduce the overhead penalty, while providing comprehensive testing of the assembly.
Another type of interface, other than the traditional interface, is known. This is the so-called Boundary Scan interface which his been used exclusively for offline testing of integrated circuit. The roots of the Boundary Scan interface are found in the scan test methodology developed in the 1960s. An example of one implementation of this technology is described in U.S. Pat. No. 3,582,902, granted Jun. 1, 1971. In addition, a standard Boundary Scan test architecture was approved by the American National Standards Institute (ANSI) and the Institute of Electrical and Electronics Engineers (IEEE) in 1990. IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standards Board, IEEE, Inc., 345 East 47th Street, New York, N.Y. 10017, USA, (1990). These publications are incorporated in their entirety herein by reference.
Historically, this standard architecture provided a means by which integrated circuits (ICs) may be designed according to the Boundary Scan standard such that their external connections may be tested using a four to six pin interface and implementation circuitry. Another application based on the standard also evolved. That is, the use of the Boundary Scan interface for offline testing of the ICs.